1. Field of the Invention
The present invention relates generally to the field of methods and circuits for analog to digital conversion. More particularly, the present invention relates to a method and circuit for analog to digital signal conversion using sigma-delta modulation of the temporal spacing between digital samples.
2. Discussion of the Related Art
Analog to Digital Converter (ADC) circuits and methods for analog to digital conversion are well-known in the art. Conventional ADCs receive an analog signal and, as a function of a reference voltage, convert the analog signal into a corresponding single or multi-bit binary level digital signal.
One type of ADC that has recently become popular is the so-called sigma-delta ADC. There are many references describing sigma-delta systems. One example is entitled Mixed-Signal Design Seminar published by Analog Devices, Inc., 1991, which is incorporated herein by reference.
AS shown in FIG. 1, a conventional sigma-delta analog to digital converter includes an analog low-pass filter 1 having a passband from zero to an upper frequency f.sub.a. The analog low-pass filter typically has a stop band frequency equal to EQU kf.sub.s /2 where f.sub.s is the sample rate
The analog low-pass filter implements a portion of a required anti-aliasing function for the ADC. The filtered analog signal is then transmitted to an analog to digital converter 2 that uses a sigma-delta modulator to convert the analog signal into a one-bit digital data stream and to noise shape the digital data stream. In A to D converters, the sigma-delta modulators are typically all analog. The sigma-delta modulator effectively low-pass filters the signal of interest and high-pass filters the quantization noise on the signal. The output of the sigma-delta modulator is typically a high frequency one-bit data stream. The A to D converter is typically clocked at a frequency kf.sub.s that is k times the sample rate (i.e., data rate or sampling frequency). This produces a so-called oversampled signal. The output of the sigma-delta modulator is transmitted to a digital low-pass filter 3 that implements the anti-aliasing function with respect to f.sub.s and has sufficient stop band attenuation at f.sub.s /2 to achieve the desired dynamic range. The digital low-pass filter removes the shaped quantization noise that resides in the upper frequency area. The output of the digital low-pass filter is transmitted to a decimator 4 that provides a data rate reduction to f.sub.s by digitally resampling the output of the digital low-pass filter. Decimation can also be viewed as the method by which the redundant information introduced by the oversampling process is removed.
One of the limitations of conventional ADCs including the sigma-delta ADC illustrated in FIG. 1 is that they only determine the magnitude of the input signal at equally spaced temporal intervals. This is known as uniform sampling. Additionally, in conventional ADCs, the sample rate, that is, the data rate f.sub.s of the digital data stream cannot be independent of the master clock that is used to clock the ADC. The digital data rate f.sub.s must be some integer division of the master clock. This means that if two different output data rates were required, for example, that are not necessarily divisible into the master clock, there must be two different frequency master clocks available for clocking the ADC.
Another problem with conventional ADCs is that they are typically not designed to be clocked by an externally supplied clock signal. The components of the ADC are typically optimized to operate at the clock frequency determined by the master clock on the ADC chip. This leads to the additional limitation that some ADCs cannot lock to and operate at some externally supplied clock signal. Therefore, if the digital data stream is supplied to some other external component that is clocked by another clock signal, since the outgoing digital data stream and the other clock signal are not necessarily related to each other (or to the master clock on the ADC), any temporal changes in the relationship between the data rate and the other clock can disrupt the entire analog to digital conversion process.
Therefore, an object of the present invention is to provide a method and apparatus for performing analog to digital conversion using non-uniform sampling (i.e., variable temporal spacing of the sampling points).
Another object of the present invention is to provide a method and apparatus for performing analog to digital conversion that can lock to an externally supplied clock signal and can provide an output signal at a sampling rate that is independent of the ADC master clock.